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Alif Semiconductor /AE302F80F5582LE_CM55_HE_View /CLKCTL_PER_MST /DPHY_PLL_CTRL0

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Interpret as DPHY_PLL_CTRL0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PLL_SOC_FORCE_LOCK)PLL_SOC_FORCE_LOCK 0 (PLL_SOC_SHADOW_CONTROL)PLL_SOC_SHADOW_CONTROL 0 (PLL_SOC_UPDATEPLL)PLL_SOC_UPDATEPLL 0 (PLL_SOC_SHADOW_CLEAR)PLL_SOC_SHADOW_CLEAR 0PLL_SOC_GMP_CNTRL 0PLL_SOC_CLKSEL 0 (PLL_SOC_GP_CLK_EN)PLL_SOC_GP_CLK_EN

Description

MIPI-DPHY PLL Control Register 0

Fields

PLL_SOC_FORCE_LOCK

Force lock to device
PLL_SOC_SHADOW_CONTROL

Selection of PLL configuration mechanism
PLL_SOC_UPDATEPLL

Control for PLL operation frequency updated
PLL_SOC_SHADOW_CLEAR

Shadow registers clear
PLL_SOC_GMP_CNTRL

Controls the effective loop-filter resistance (=1/gmp) to increase/decrease MPLL bandwidth
PLL_SOC_CLKSEL

CLKEXT divider selection
PLL_SOC_GP_CLK_EN

Enable signal for CLKOUT_GP clock

Links

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data